A pipeline with respect to a computer is the continuous and somewhat overlapped movement of data to a processor. Pipelining is the use of a pipeline. Without a pipeline, a computer processor gets the first instruction from memory, performs the operation it calls for, and then goes to get the next instruction from memory. While fetching (getting) the instruction, the arithmetic and logic unit (ALU) of the processor is idle. The processor usually has to wait until it gets the next instruction.
With pipelining, a computer architecture allows the next instructions to be fetched while the processor is performing arithmetic operations, holding them in a buffer close to the processor until each instruction operation can be performed. The staging of instruction fetching is continuous. The result is an increase in the number of instructions that can be performed during a given time period.
Computer processor pipelining is sometimes divided into an instruction pipeline and an arithmetic pipeline. The instruction pipeline represents the stages in which an instruction is moved through the processor, including its being fetched, perhaps buffered, and then executed. The arithmetic pipeline represents the parts of an arithmetic operation that can be broken down and overlapped as they are performed.
Pipelines and pipelining also apply to computer memory controllers and moving data through various memory staging places. Data may be pipelined (written or read) to banks of memory when the memory addresses have some order. For example, writing or reading data that have consecutive addresses allows data to be pipelined from different memory banks. However, when a non-sequential read or write occurs, data pipelining is interrupted and the full access time of the memory is required to complete the read or write of the memory. The access time may be 3 or 4 clock cycles for example.
Because the read access time of memory may not be known until the memory is fabricated, the read latency (the number of clock cycles needed to access the data from memory) time may not be known until the memory is fabricated. After the memory if fabricated, a longer read latency than calculated may be needed because the memory is slower than expected due to variations of parameters in the process (e.g. threshold voltages, the length of transistors, capacitance values etc.) of fabrication or a shorter read latency than calculated may be needed because the memory is faster than expected due to variations of parameters in the process of fabrication.
A memory controller, in order to make efficient use of pipelining in memory, needs to “know” the actual read access time of memory. When the actual read access of the memory is known, a controller can allocate the number of clock cycles needed for read latency of a fabricated pipelined memory array. A memory controller that can be programmed based on actual measured read access times of fabricated memories can improve the speed at which data may be accessed in memory.